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may 2011 FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 1 www.fairchildsemi.com FDMS7606 rev.c FDMS7606 dual n-channel powertrench ? mosfet q1: 30 v, 12 a, 11.4 m q2: 30 v, 22 a, 11.6 m features q1: n-channel ? max r ds(on) = 11.4 m at v gs = 10 v, i d = 11.5 a ? max r ds(on) = 15.7 m at v gs = 4.5 v, i d = 10 a q2: n-channel ? max r ds(on) = 11.6 m at v gs = 10 v, i d = 12 a ? max r ds(on) = 17.2 m at v gs = 4.5 v, i d = 9.5 a ? rohs compliant general description this device includes two specialized n-channel mosfets in a dual mlp package. the switch node has been internally connected to enable easy placement and routing of synchronous buck converters. the contro l mosfet (q1) and synchronous mosfet (q2) have been designed to provide optimal power efficiency. applications ? computing ? communications ? general purpose point of load ? notebook charger power 56 s2 s2 s2 g2 d1 d1 d1 g1 d1 s1/d2 top bottom pin1 s2 s2 s2 g2 d1 d1 d1 g1 4 3 2 1 5 6 7 8 q2 q1 mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 30 30 v v gs gate to source voltage (note 3) 20 20 v i d drain current -continuous (package limited) t c = 25 c 12 22 a -continuous (silicon limited) t c = 25 c 41 39 -continuous t a = 25 c 11.5 1a 12 1b -pulsed 50 60 e as single pulse avalanche energy (note 4) 25 33 mj p d power dissipation for single operation t a = 25c 2.2 1a 2.5 1b w power dissipation for single operation t a = 25c 1.0 1c 1.0 1d t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient 57 1a 50 1b c/w r ja thermal resistance, junction to ambient 125 1c 120 1d r jc thermal resistance, junction to case 4.6 4.7 device marking device package reel size tape width quantity FDMS7606 FDMS7606 power 56 13 ? 12 mm 3000 units
FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 2 www.fairchildsemi.com FDMS7606 rev.c electrical characteristics t j = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v q1 q2 30 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25c q1 q2 16 20 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v q1 q2 1 1 a i gss gate to source leakage curent v gs = 20 v, v ds = 0 v v gs = 20 v, v ds = 0 v q1 q2 100 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a q1 q2 1.0 1.0 2.1 1.9 3.0 3.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25c q1 q2 -6 -5.5 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 11.5 a v gs = 4.5 v, i d = 10 a v gs = 10 v, i d = 11.5 a, t j = 125c q1 9.2 12.6 11.8 11.4 15.7 14.7 m v gs = 10 v, i d = 12 a v gs = 4.5 v, i= 9.5 a v gs = 10 v, i d = 12 a, t j = 125c q2 9.7 12.8 12.3 11.6 17.2 15.4 g fs forward transconductance v dd = 5 v, i d = 11.5 a v dd = 5 v, i d = 12 a q1 q2 53 47 s c iss input capacitance q1: v ds = 15 v, v gs = 0 v, f = 1 mhz q2: v ds = 15 v, v gs = 0 v, f = 1 mhz q1 q2 1050 947 1400 1260 pf c oss output capacitance q1 q2 295 191 395 255 pf c rss reverse transfer capacitance q1 q2 32 131 50 200 pf r g gate resistance q1 q2 0 . 2 0.2 1.6 1.0 4 . 0 2.5 t d(on) turn-on delay time q1 v dd = 15 v, i d = 11.5 a, r gen = 6 q2 v dd = 15 v, i d = 12 a, r gen = 6 q1 q2 7 6 14 12 ns t r rise time q1 q2 3 3 10 10 ns t d(off) turn-off delay time q1 q2 18 19 33 34 ns t f fall time q1 q2 3 3 10 10 ns q g(tot) total gate charge v gs = 0v to 10 v q1 v dd = 15 v, i d = 11.5 a q1 q2 16 19 22 27 nc q g(tot) total gate charge v gs = 0v to 5 v q1 q2 8 10 11 15 nc q gs gate to source charge q2 v dd = 15 v, i d = 12 a q1 q2 3.2 2.6 nc q gd gate to drain ?miller? charge q1 q2 2.0 4.2 nc
FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 3 www.fairchildsemi.com FDMS7606 rev.c electrical characteristics t j = 25c unless otherwise noted drain-source diod e characteristics symbol parameter test conditions type min typ max units v sd source-drain diode forward voltage v gs = 0 v, i s = 2 a (note 2) v gs = 0 v, i s = 11.5 a (note 2) v gs = 0 v, i s = 2 a (note 2) v gs = 0 v, i s = 12 a (note 2) q1 q1 q2 q2 0.76 0.87 0.75 0.85 1.2 1.2 1.2 1.2 v t rr reverse recovery time q1 i f = 11.5 a, di/dt = 100 a/s q2 i f = 12 a, di/dt = 100 a/s q1 q2 22 18 35 33 ns q rr reverse recovery charge q1 q2 7 6 13 12 nc notes: 1.r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. as an n-ch device, the negative vgs rating is for low du ty cycle pulse occurrence only. no continuous rating is implied 4. q1: e as of 25 mj is based on starting t j = 25 o c, l = 0.3 mh, i as = 13 a, v dd = 27 v, v gs = 10 v. q2: e as of 33 mj is based on starting t j = 25 o c, l = 0.3 mh, i as = 15 a, v dd = 27 v, v gs = 10 v. a. 57 c/w when mounted on a 1 in 2 pad of 2 oz copper c. 125 c/w when mounted on a minimum pad of 2 oz copper b. 50 c/w when mounted on a 1 in 2 pad of 2 oz copper d. 120 c/w when mounted on a minimum pad of 2 oz copper
FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 4 www.fairchildsemi.com FDMS7606 rev.c typical characteristics (q1 n-channel) t j = 25c unless otherwise noted figure 1. 0.00.51.01.52.0 0 10 20 30 40 50 v gs = 6 v v gs = 4 v v gs = 10 v v gs = 4.5 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 1020304050 0 1 2 3 4 5 v gs = 6 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 11.5 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 8 16 24 32 t j = 125 o c i d = 11.5 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 10 20 30 40 50 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 50 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 5 www.fairchildsemi.com FDMS7606 rev.c figure 7. 0 3 6 9 12 15 18 0 2 4 6 8 10 i d = 11.5 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 40 1 10 20 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 10 20 30 40 50 r t jc = 4.6 o c/w v gs = 4.5 v limited by package v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100200 0.01 0.1 1 10 60 100 p s dc 100 ms 10 ms 1 ms 1s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c 10s figure 12. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 500 single pulse r t ja = 125 o c/w p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 6 www.fairchildsemi.com FDMS7606 rev.c figure 13. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 2 single pulse r t ja = 125 o c/w (note 1c) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transi ent thermal response curve typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMS7606 rev.c typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 14. on-region characteristics figure 15. normalized on-resist ance vs drain current and gate voltage figure 16. normalized on-resistance vs junction temperature figure 17. on-resistance vs gate to source voltage figure 18. transfer characteristics figure 19. source to drain diode forward voltage vs source current 0.00.51.01.52.0 0 10 20 30 40 50 60 v gs = 4 v v gs = 6 v v gs = 10 v v gs = 4.5 v v gs = 3.5 v pulse duration = 80 s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) 0 102030405060 0 1 2 3 4 5 v gs = 6 v v gs = 3.5 v pulse duration = 80 s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 10 v -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 12 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 4 8 12 16 20 24 28 32 36 40 t j = 125 o c i d = 12 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m pulse duration = 80 s duty cycle = 0.5% max 12345 0 10 20 30 40 50 60 t j = 150 o c v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 8 www.fairchildsemi.com FDMS7606 rev.c typical characteristi cs (q2 n-channel) t j = 25c unless otherwise noted figure 20. gate charge characteristics figure 21. capacitance vs drain to source voltage figure 22. unclamped inductive switching capability f i g u r e 2 3 . m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 2 4 . f o r w a r d b i a s s a f e operating area figure 25. single pulse maximum power dissipation 0 5 10 15 20 0 2 4 6 8 10 i d = 12 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v 0.1 1 10 30 50 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 0.001 0.01 0.1 1 10 40 1 10 30 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) 25 50 75 100 125 150 0 10 20 30 40 limited by package r jc = 4.7 o c/w v gs = 4.5 v v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) 0.01 0.1 1 10 100200 0.01 0.1 1 10 70 100 s dc 100 ms 10 ms 1 ms 1s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r ja = 120 o c/w t a = 25 o c 10s 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 500 single pulse r ja = 120 o c/w p ( pk ) , peak transient power (w) t, pulse width (sec)
typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 26. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 2 single pulse r t ja = 120 o c/w (note 1d) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 9 www.fairchildsemi.com FDMS7606 rev.c
FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 10 www.fairchildsemi.com FDMS7606 rev.c dimensional outlin e and pad layout 6. 30 0.63 1.27 1. 27 (opti on 2 - isolated leads) (opti on 1 - fused l eads 5,6 ,7) 0.20 0.340 4 x r ecomm end ed la nd pat t ern 2. 67 4.00 0. 65 t yp 12 3 4 5 6 7 8 0.92 0. 66 0.54 0.40 0.65 (5x) 0.63 3. 81 1. 27 6.0 5. 0 pin# 1 quadrant 0.80 max 0. 25 0 b. dimensions are in mill imeters. c. dimensions and tolerances per e. drawing file name : mkt-mlp08prev1 a. does not ful ly conform to jedec regist rat ion, m o- 229. asme y14. 5m, 19 94 top view b ottom view r ecomm end ed la nd pat t ern 0. 08 c b a 0. 10 c 2x 0.10 c 2x side vi ew (0.20 ) seating pl ane 0. 10 c a b 0.10 c 12 3 4 5 6 7 8 6. 30 2. 67 4.00 0. 65 t yp pin #1 ident 0. 05 c 1 2 3 4 5 6 7 8 0. 05 0. 00 2.72 2.62 3. 85 3. 75 0. 48 0. 38 (5x) 0. 97 0. 87 0.56 0.46 (5 x) 0.92 0. 66 0. 66 0. 55 0.54 0.40 0.45 d. l and patt ern rec ommen dat ion is based on fsc design only
FDMS7606 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 11 www.fairchildsemi.com FDMS7606 rev.c anti-counterfeiting policy fairchild semiconductor corporation?s anti-counterfeiting policy. fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in the industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts experi ence many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing del ays. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourage s customers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. ? trademarks the following includes registered and unregistered trademarks and se rvice marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical co mponents in life support devices or systems without the express written approval of fa irchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life sup port device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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